Performance evaluation for hybrid architectures

• Authors: Roger Chamberlain;Praveen Krishnamurthy
• Venue: Performance evaluation for hybrid architectures
• Year: 2006

In this dissertation we discuss methodologies for estimating the performance of applications on hybrid architectures, systems that include various types of computing resources (e.g., traditional general-purpose processors, chip multiprocessors, reconfigurable hardware). A common use of hybrid architectures is to deploy stages of pipelined applications on "suitable" compute units. The first problem we focus on is the sizing of data queues between the different processing elements in a hybrid system. The discussion centers on our analytical models that can be used to derive performance metrics of interest, such as throughput and stalling probability for networks of processing elements with finite data buffering between them. We then discuss the reliability of the performance models. We start by presenting scenarios where our analytical model is reliable, and then introduce tests that can detect its inapplicability. Once we transition into the question of reliability of performance models, we assess the accuracy and applicability of various evaluation methods. We present results from our experiments to show the need for measuring and accounting for operating system effects in architectural modeling and estimation. We also point to a lack in the ability of current estimation methods (primarily simulation-based methods) to detect and analyze rare events in application execution. We use this and typical embedded benchmarks to demonstrate the ability and ease of emulation-based performance analysis. We use BLASTN, a biosequence similarity search program, as our running example of a pipelined application in the dissertation. We present Mercury BLASTN, a reconfigurable hybrid system developed to accelerate BLASTN. We also use the performance evaluation techniques developed in this dissertation to aid in the performance estimates for Mercury BLASTN.