Empirical performance assessment using soft-core processors on reconfigurable hardware

  • Authors:
  • Richard Hough;Praveen Krishnamurthy;Roger D. Chamberlain;Ron K. Cytron;John Lockwood;Jason Fritts

  • Affiliations:
  • Washington University, St. Louis, Missouri;Washington University, St. Louis, Missouri;Washington University, St. Louis, Missouri;Washington University, St. Louis, Missouri;Washington University, St. Louis, Missouri;Saint Louis University, St. Louis, Missouri

  • Venue:
  • Proceedings of the 2007 workshop on Experimental computer science
  • Year:
  • 2007

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Abstract

Simulation has been the de facto standard method for performance evaluation of newly proposed ideas in computer architecture for many years. While simulation allows for theoretically arbitrary fidelity (at least to the level of cycle accuracy) as well as the ability to monitor the architecture without perturbing the execution itself, it suffers from low effective fidelity and long execution times. We (and others) have advocated the use of empirical experimentation on reconfigurable hardware for computer architecture performance assessment. In this paper, we describe an empirical performance assessment subsystem implemented in reconfigurable hardware and illustrate its use. Results are presented that demonstrate the need for the types of performance assessment that reconfigurable hardware can provide.