Formal verification of parallel programs
Communications of the ACM
Introduction to VLSI Systems
Automatic Verification of Sequential Circuits Using Temporal Logic
IEEE Transactions on Computers
Structured Specification of Communicating Systems
IEEE Transactions on Computers
25 Years of Model Checking
A logical approach to data-aware automated sequence generation
Transactions on Computational Science XV
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The use of temporal logic for the specification of hardware modules is explored. Temporal logic is an extension of conventional logic. While traditional logic is useful for specifying combinational circuits, it is shown how the extensions of temporal logic apply to the specification of memory, as well as the safeness and liveness properties of active circuits representing processes. These ideas are demonstrated by the example of a self-timed arbiter. An implementation of the arbiter is also given, and its formal verification by a kind of reachability analysis is discussed. This verification approach is also useful for finding design errors, as demonstrated by an example.