On an Optimally Fault-Tolerant Multiprocessor Network Architecture
IEEE Transactions on Computers
Distributed fault-tolerance for large multiprocessor systems
ISCA '80 Proceedings of the 7th annual symposium on Computer Architecture
De bruijn communications networks.
De bruijn communications networks.
Graphs and Hypergraphs
Performance Analysis of STC104 Interconnection Networks
HPC-ASIA '97 Proceedings of the High-Performance Computing on the Information Superhighway, HPC-Asia '97
| Hi-index | 14.98 |
A synthesis approach to the design of a class of regular networks which provide optimal fault tolerance and are of small diameter is presented. The approach makes it possible to design a regular network in the form of a directed graph when the number of nodes n and the number of connections per node d are given, for any n and d. The designed graph will have node connectivity d and a diameter proportional to (og/sub d/ n).