Performance Analysis of STC104 Interconnection Networks

Authors:
Hyo Jong Lee;Byeong Yeol Song
Affiliations:
-;-
Venue:
HPC-ASIA '97 Proceedings of the High-Performance Computing on the Information Superhighway, HPC-Asia '97
Year:
1997

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Abstract

The fast routing chip, Inmos STC104 has been designed and now available in the market. Many research results about the switch have been presented and are currently under evaluation concerning the performance, design cost and scalability of the packet switch. There is a great demand for an efficient and reliable router in high performance parallel processing systems or data management networks. The performance and characteristics of each different network topology, such as multistage networks, meshes, tori, and N-cubes are vital information to make decision on an appropriate network. This paper reviews the technology utilized in a fast packet switch STC104 and studies reliable routing algorithms for various network configurations. The performance of each different configuration is also studied and compared.