Parallelization schemes for memory optimization on the cell processor: a case study of image processing algorithm

Authors:
Tarik Saidani;Stéphane Piskorski;Lionel Lacassagne;Samir Bouaziz
Affiliations:
Institut d'Electronique, Fondamentale, Orsay, France;Laboratoire de Recherche en, Informatique, Orsay, France;Institut d'Electronique, Fondamentale, Orsay, France;Institut d'Electronique, Fondamentale, Orsay, France
Venue:
MEDEA '07 Proceedings of the 2007 workshop on MEmory performance: DEaling with Applications, systems and architecture
Year:
2007

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Abstract

The Cell processor is a typical example of a heterogeneous multiprocessor on-chip architecture that uses several levels of parallelism to deliver high performance. Reducing the gap between peak performance and effective performance is the challenge for software tool developers and the application developers. Image processing and media applications are typical "main stream" applications. We use the Harris algorithm for detection of Points of Interest in an image as a benchmark to compare the performance of several parallel schemes on a Cell processor. The impact of the DMA controlled data transfers and the synchronizations between SPEs explains the differences between the performance of the different parallelization schemes. These results will be used to design a tool for an efficient mapping of image processing applications on multi-core architectures.