Reducing leakage power with BTB access prediction
Integration, the VLSI Journal
A dual-mode architecture for fast-switching STT-RAM
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
Process variation aware data management for STT-RAM cache design
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
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Nowadays, embedded systems can be found in a wide range of pervasive devices (e.g., smart phones, PDAs, or video/digital cameras). These devices contain large cache memories, whose power consumption can reach about 50% of the total spent energy, from which leakage energy is the predominant fraction in current technologies. This paper proposes a technique to reduce leakage energy consumption in data caches on embedded systems, which is based on the fact that most stored bits take a logical value of zero. The proposed technique has been evaluated on a model of a con- temporary high-end embedded microprocessor, namely the ARM Cortex A8 processor, executing a set of standard em- bedded benchmarks. Experimental results show that leak- age energy savings reach about 40% with no IPC loss.