A check-points extraction method for formal verification

Authors:
Chikatoshi Yamada;Yasunori Nagata
Affiliations:
Okinawa National College of Tech., Dept. of Inf. Comm. Syst. Eng., Okinawa, Japan;Univ. of the Ryukyus, Dept. of Electrical & Electronics Eng., Okinawa, Japan
Venue:
ISTASC'07 Proceedings of the 7th Conference on 7th WSEAS International Conference on Systems Theory and Scientific Computation - Volume 7
Year:
2007

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Abstract

In design of complex and large scale systems, formal verification has played an important role. However, it is inefficiency to verify the entire systems. This article considers the case where designers of systems can extract check-points easily in formal verification. Moreover, we propose a method by which temporal formulas can be obtained inductively for specifications in formal verification.