Parallel algorithms for robot path planning with simpler VLSI architecture

Authors:
Michael Arock;R. Ponalagusamy
Affiliations:
Department of Computer Applications, National Institute of Technology, Tiruchirappalli 620 015, Tamilnadu, India.;Department of Mathematics, National Institute of Technology, Tiruchirappalli 620 015, Tamilnadu, India
Venue:
International Journal of Computer Applications in Technology
Year:
2006

Citing 7
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Abstract

This paper proposes a parallel algorithm for robot path planningon a linear array with a reconfigurable pipelined bus system(LARPBS) through the construction of a Voronoi diagram on a binaryimage of the workspace. The algorithm is based on a d4distance metric, and it does not incur any additional time orprocessor requirements compared with those of a previously reportedproposal (Tzionas et al., 1997). This paper recommends the samemodel as the simpler VLSI architecture for the problem inquestion.