Memory-efficient and high-performance parallel-pipelined architectures for 5/3 forward and inverse discrete wavelet transform

Authors:
Tze-Yun Sung
Affiliations:
Department of Microelectronics Engineering, Chung Hua University, Hsinchu, Taiwan
Venue:
MUSP'07 Proceedings of the 7th WSEAS International Conference on Multimedia Systems & Signal Processing
Year:
2007

Citing 7
Cited 1

The Verilog Hardware Description Language, 5th Edition

The Verilog Hardware Description Language, 5th Edition
Multiresolution Signal Decomposition: Transforms, Subbands, and Wavelets

Multiresolution Signal Decomposition: Transforms, Subbands, and Wavelets
A VLSI architecture for lifting-based forward and inverse wavelettransform

IEEE Transactions on Signal Processing
High speed lattice based VLSI architecture of 2D discrete wavelet transform for real-time video signal processing

IEEE Transactions on Consumer Electronics
High performance scalable image compression with EBCOT

IEEE Transactions on Image Processing
Scalable wavelet coding for synthetic/natural hybrid images

IEEE Transactions on Circuits and Systems for Video Technology
An efficient architecture for two-dimensional discrete wavelet transform

IEEE Transactions on Circuits and Systems for Video Technology

Wavelet filter design based on the lifting scheme and its application in lossless image compression

WSEAS Transactions on Signal Processing

Quantified Score

Hi-index	0.00

Visualization

Abstract

In this paper, high-efficient lifting-based architectures for the 5/3 forward and inverse discrete wavelet transform (DWT) are proposed. The proposed parallel and pipelined architecture consists of a horizontal filter (HF) and a vertical filter (VF). The system delays of the proposed architectures are reduced. Filter coefficients of the biorthogonal 5/3 wavelet low-pass filter are quantized before implementation in the high-speed computation hardware. In the proposed architectures, all multiplications are performed using less shifts and additions. The proposed parallel-pipelined architectures are 100% hardware utilization and ultra low-power. The architectures have regular structure, simple control flow, high throughput and high scalability. Thus, they are very suitable for new-generation image compression systems, such as JPEG-2000.