High speed lattice based VLSI architecture of 2D discrete wavelet transform for real-time video signal processing

Authors:
Taegeun Park;Sunkyung Jung
Affiliations:
Comput. & Electron. Eng., Catholic Univ. of Korea, Bucheon, South Korea;-
Venue:
IEEE Transactions on Consumer Electronics
Year:
2002

Citing 0
Cited 2

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Memory-efficient and high-performance parallel-pipelined architectures for 5/3 forward and inverse discrete wavelet transform

MUSP'07 Proceedings of the 7th WSEAS International Conference on Multimedia Systems & Signal Processing

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Abstract

This paper presents an efficient lattice structure based VLSI architecture of 2D discrete wavelet transform (DWT) for hierarchical image compression, which is scalable to extend to an arbitrary 2D DWT with M laps and J levels. The proposed architecture consists Of four 1D lattice filters, which processes in horizontal and vertical directions at the same time. The proposed lattice structure fits in a VLSI implementation due to its regularity and shows the period of N2/2 to compute an N×N image because the even and odd rows are processed simultaneously. Compared to conventional approaches, the proposed architecture shows shorter period to complete 2D DWT while requiring relatively less hardware resources. Therefore, the proposed architecture can be applied in real-time video signal processing such as JPEG-2000 and MPEG4, which require high speed processing. The process schedule using the data dependency graph, performance, and the required hardware cost are discussed.