Design of a spintronic arithmetic and logic unit using magnetic tunnel junctions

Authors:
Shruti R. Patil;Xiaofeng Yao;Hao Meng;Jian-Ping Wang;David J. Lilja
Affiliations:
University of Minnesota Twin Cities, Minneapolis, MN, USA;University of Minnesota Twin Cities, Minneapolis, MN, USA;University of Minnesota Twin Cities, Minneapolis, MN, USA;University of Minnesota Twin Cities, Minneapolis, MN, USA;University of Minnesota Twin Cities, Minneapolis, MN, USA
Venue:
Proceedings of the 5th conference on Computing frontiers
Year:
2008

Citing 1
Cited 1

Development of the magnetic tunnel junction MRAM at IBM: from first junctions to a 16-Mb MRAM demonstrator chip

IBM Journal of Research and Development - Spintronics

A programmable and scalable technique to design spintronic logic circuits based on magnetic tunnel junctions

Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI

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Abstract

Conventional electronics technology uses an electron's charge to store information and a current of electrons to transfer information. Spintronics technology, in contrast, uses an electron's 'spin' in addition to its charge to transfer and store information. Magnetic Tunnel Junctions (MTJ) are spintronic devices that exhibit two distinct resistance states due to the tunneling magnetoresistance (TMR) effect. Their properties can provide significant advantages over conventional electronics in the design of computer systems. We characterize some of the challenges in using spintronic technology in large systems, and describe a novel design technique called 'union with neutralization' to combine individual component designs into multi-functional units. We use this technique to present the design of an arithmetic and logical unit (ALU) using 20 MTJs and two CMOS-based sense amplifiers. The spintronics-based ALU has the potential to offer considerable area, timing, and power advantages over a conventional CMOS-based ALU.