Soft-error resilience of the IBM POWER6 processor input/output subsystem
IBM Journal of Research and Development
Self-adaptive system for addressing permanent errors in on-chip interconnects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design techniques for cross-layer resilience
Proceedings of the Conference on Design, Automation and Test in Europe
A middleware approach to achieving fault tolerance of Kahn process networks on networks on chips
International Journal of Reconfigurable Computing - Special issue on selected papers from the international workshop on reconfigurable communication-centric systems on chips (ReCoSoC' 2010)
Operating system support for redundant multithreading
Proceedings of the tenth ACM international conference on Embedded software
Who watches the watchmen? - protecting operating system reliability mechanisms
HotDep'12 Proceedings of the Eighth USENIX conference on Hot Topics in System Dependability
Breaking the energy barrier in fault-tolerant caches for multicore systems
Proceedings of the Conference on Design, Automation and Test in Europe
Replicating tag entries for reliability enhancement in cache tag arrays
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of the coarse-grained reconfigurable architecture DART with on-line error detection
Microprocessors & Microsystems
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The IBM Power6 microprocessor extends the capabilities of the Power5, dramatically increasing its ability to recover from hard and soft errors without increasing system downtime. The Power6 adds new mainframe-like features for enhanced reliability, availability, and serviceability, including instruction retry and processor failover. Optimized for performance and power, the Power6 implements these RAS enhancements without compromising ultrahigh-frequency operation.