A 3.2Gb/s clock and data recovery circuit without reference clock for a high-speed serial data link

  • Authors:

  • Kang jik Kim;Ki sang Jeong;Seong ik Cho

  • Affiliations:

  • The Department of Electronics Engineering, Chonbuk National University, Jeonju, Jeonbuk, South Korea;The Department of Electronics Engineering, Chonbuk National University, Jeonju, Jeonbuk, South Korea;The Department of Electronics Engineering, Chonbuk National University, Jeonju, Jeonbuk, South Korea

  • Venue:
  • CISST'08 Proceedings of the 2nd WSEAS International Conference on Circuits, Systems, Signal and Telecommunications
  • Year:
  • 2008

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Abstract

A 3.2Gb/s clock and data recovery (CDR) circuit for a high-speed serial link without the reference clock is described. The CDR has a phase and frequency detector (PD and FD), which incorporates a half-rate bang-bang type oversampling PD and a half-rate frequency detector that can achieve low-jitter operation and improve pull-in range. The PD of oversamping method finds a phase error by generating four phase up/down signals. The FD also finds a frequency error by generating frequency up/down signals. Therefore these six signals control three charge pump (CP) respectively. It also has a ring oscillator type voltage controlled oscillator (VCO) and three charge pumps. The VCO consists of four fully differential delay cells with rail-to-rail current bias scheme that can increase the VCO tuning range and tuning linearity and each delay cell has a duty-cycle circuit(DCC) as a buffer of the duty-cycle mismatch compensation. The CDR circuit was designed for fabrication using 0.18um 1P6M CMOS process. The designed circuit consumes 148mW from 1.8V supply voltage according to simulation results.