MOSFET Models for VLSI Circuit Simulation: Theory and Practice
MOSFET Models for VLSI Circuit Simulation: Theory and Practice
MOSFET Modeling and Bsim3 User's Guide
MOSFET Modeling and Bsim3 User's Guide
Design and optimization of ÷8/9 divider in PLL frequency synthesizer with dynamic logic (E_TSPC)
EHAC'07 Proceedings of the 6th WSEAS International Conference on Electronics, Hardware, Wireless and Optical Communications
A 60-GHz broad-band frequency divider in 0.13-µm CMOS
IMCAS'07 Proceedings of the 6th WSEAS International Conference on Instrumentation, Measurement, Circuits and Systems
A 3.2Gb/s clock and data recovery circuit without reference clock for a high-speed serial data link
CISST'08 Proceedings of the 2nd WSEAS International Conference on Circuits, Systems, Signal and Telecommunications
Design of Analog CMOS Integrated Circuits
Design of Analog CMOS Integrated Circuits
Design and analysis of a second order phase locked loops (PLLs)
TELE-INFO'06 Proceedings of the 5th WSEAS international conference on Telecommunications and informatics
| Hi-index | 0.00 |
A highly power supply independent Ring Oscillator architecture is proposed in this paper. The proposed architecture is achieved using the advantages of best previous techniques. Making use of opposite characteristics of the delay cells along with power supply isolation and self-biasing have resulted in a nearly 1% sensitivity; a record better than all previous architectures. To accomplish such robustness, different delay stages with different characteristics have been used in the proposed architecture. Simulations based on 0.5µm CMOS technology confirm robustness of the proposal.