CDMA: principles of spread spectrum communication
CDMA: principles of spread spectrum communication
RF microelectronics
A survey of CORDIC algorithms for FPGA based computers
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Power estimation methods for analog circuits for architectural exploration of integrated systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Digital Communication Receivers: Synchronization, Channel Estimation, and Signal Processing
Digital Communication Receivers: Synchronization, Channel Estimation, and Signal Processing
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We determine the optimal allocation of power between the analog and digital sections of an RF receiver, while meeting the BER constraint. Unlike conventional RF receiver designs, we treat the SNR at the output of the analog front end (SNRAD) as a design parameter rather than a specification to arrive at this optimal allocation. We first determine the relationship of the SNRAD to the resolution and operating frequency of the digital section. We then use power models for the analog and digital sections to solve the power minimization problem. As an example, we consider a 802.15.4 compliant low-IF receiver operating at 2.4 GHz in 0.13μm technology with 1.2 V power supply. We find that the overall receiver power is minimized by having the analog front end provide an SNR of 1.3dB and the ADC and the digital section operate at 1-bit resolution with 18MHz sampling frequency while achieving a power dissipation of 7mW.