Pipeline gating: speculation control for energy reduction
Proceedings of the 25th annual international symposium on Computer architecture
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
Saving energy with just in time instruction delivery
Proceedings of the 2002 international symposium on Low power electronics and design
Proceedings of the 10th international conference on Architectural support for programming languages and operating systems
Dynamic dead-instruction detection and elimination
Proceedings of the 10th international conference on Architectural support for programming languages and operating systems
On Reducing Register Pressure and Energy in Multiple-Banked Register Files
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Energy-efficient issue queue design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Instruction Scheduling for Low Power
Journal of VLSI Signal Processing Systems
A Simple Mechanism for Detecting Ineffectual Instructions in Slipstream Processors
IEEE Transactions on Computers
Power-Efficient Wakeup Tag Broadcast
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Dynamic Resizing of Superscalar Datapath Components for Energy Efficiency
IEEE Transactions on Computers
Energy-aware code motion for GPU shader processors
ACM Transactions on Embedded Computing Systems (TECS)
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An important approach to reduce power dissipation is reducing the number of instructions executed by the processor. To achieve this goal, this paper introduces a novel instruction scheduling algorithm that executes an instruction only when its result is required by another instruction. In this manner, it not only does not execute useless instructions, but also reduces the number of instructions executed after a mispredicted branch. The cost of the extra hardware is 161 bytes for 128 instruction window size. Measurements done using SPEC CPU 2000 benchmarks show that the average number of executed instructions is reduced by 13.5% while the average IPC is not affected.