Theoretical Computer Science
Model checking
Introduction to Formal Hardware Verification: Methods and Tools for Designing Correct Circuits and Systems
Duration Calculus: A Formal Approach to Real-Time Systems (Monographs in Theoretical Computer Science. an Eatcs Seris)
System Analysis, Design, and Development: Concepts, Principles, and Practices (Wiley Series in Systems Engineering and Management)
Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems
Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems
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Verifying functional models is state of the art in the electronic design automation (eda) industry. Improved methods enable the application in industry sized projects. These methods basically work on a detailed state model, properties must be expressible on states. On system level, behavior is expressed in terms of (timed) transactions between functional or architectural artifacts of the design. While recent model checking methods use some workarounds to map transaction models onto state models, we present an alternative approach with an extended system model to verify transaction properties.