The design and analysis of VLSI circuits
The design and analysis of VLSI circuits
Can Redundancy and Masking Improve the Performance of Synchronizers?
IEEE Transactions on Computers
Comments on 'Can Redundancy and Masking Improve the Performance of Synchronizers?'
IEEE Transactions on Computers
An Engineering Approach to Digital Design
An Engineering Approach to Digital Design
Analysis and Design of Analog Integrated Circuits
Analysis and Design of Analog Integrated Circuits
Noise Modeling Effects in Redundant Synchronizers
IEEE Transactions on Computers
Oscillatory Metastability in Optical Network Synchronizer Circuits
The Journal of Supercomputing
A Low-Cost Jitter Measurement Technique for BIST Applications
Journal of Electronic Testing: Theory and Applications
| Hi-index | 14.98 |
A synchronizer timing model, called the jitter model, which has general application to metastable reliability analysis, is proposed and analyzed. The jitter model is applied to show that redundancy cannot improve the metastable reliability of synchronizers, contradicting previous work by A. El-Amawy. The jitter model extends previous synchronizer input timing models by incorporating the effects of circuit noise. The circuit noise translates into jitter or random time displacement of a previously proposed deterministic aperture mode. The jitter model is supported by simulation, circuit analysis, and experimental work. The results of a SPICE simulation of a CMOS D-type flip-flop are presented. An experimental bistable device is constructed to examine the behavior of synchronizers with noise. Statistical results obtained from the experimental bistable device support the jitter model for metastability. The sensitivity of metastable reliability of redundant synchronizers to modeling assumptions is highlighted.