Equivalent Semantic Translation from Parallel DEVS Models to Time Automata

Authors:
Shoupeng Han;Kedi Huang
Affiliations:
College of Mechaeronics Engineering and Automation, National University of Defense Technology, 410073, Changsha Hunan, China;College of Mechaeronics Engineering and Automation, National University of Defense Technology, 410073, Changsha Hunan, China
Venue:
ICCS '07 Proceedings of the 7th international conference on Computational Science, Part I: ICCS 2007
Year:
2007

Citing 3
Cited 2

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Abstract

Dynamic reconfigurable simulation based on Discrete Event System Specification (DEVS) requires efficient verification of simulation models. Traditional verification method of DEVS model is based on I/O test in which a DEVS model is regarded as a black box or a grey box. This method is low efficient and insufficient because input samples are often limited. This paper proposes a formal method which can translate Parallel DEVS model into a restrict kind of Timed Automata (TA) with equivalent behaviors. By this translation, a formal verification problem of Parallel DEVS model can be changed into the formal verification of according timed automata.