Theoretical Computer Science
Visual modeling of DEVS-based multiformalism systems based on higraphs
WSC '93 Proceedings of the 25th conference on Winter simulation
Theory of Modeling and Simulation
Theory of Modeling and Simulation
A Real-Time Discrete Event System Specification Formalismfor Seamless Real-Time Software Development
Discrete Event Dynamic Systems
Dynamical Properties of Timed Automata
Discrete Event Dynamic Systems
CD++: a toolkit to develop DEVS models
Software—Practice & Experience
Decidability and Complexity Results for Timed Automata and Semi-linear Hybrid Automata
HSCC '00 Proceedings of the Third International Workshop on Hybrid Systems: Computation and Control
HART '97 Proceedings of the International Workshop on Hybrid and Real-Time Systems
Simulation and verification II: from timed automata to DEVS models
Proceedings of the 35th conference on Winter simulation: driving innovation
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Concurrency Theory: Calculi an Automata for Modelling Untimed and Timed Concurrent Systems
Concurrency Theory: Calculi an Automata for Modelling Untimed and Timed Concurrent Systems
Formal Software Analysis Emerging Trends in Software Model Checking
FOSE '07 2007 Future of Software Engineering
Testing software components for integration: a survey of issues and techniques: Research Articles
Software Testing, Verification & Reliability
Predictable real-time software synthesis
Real-Time Systems
Random testing: from the classical approach to a global view and full test automation
Proceedings of the 2nd international workshop on Random testing: co-located with the 22nd IEEE/ACM International Conference on Automated Software Engineering (ASE 2007)
A formal verification approach for DEVS
Proceedings of the 2007 Summer Computer Simulation Conference
eCD++: an engine for executing DEVS models in embedded platforms
Proceedings of the 2007 Summer Computer Simulation Conference
On conciseness of extensions of timed automata
Journal of Automata, Languages and Combinatorics
Equivalent Semantic Translation from Parallel DEVS Models to Time Automata
ICCS '07 Proceedings of the 7th international conference on Computational Science, Part I: ICCS 2007
Discrete-Event Modeling and Simulation: A Practitioner's Approach
Discrete-Event Modeling and Simulation: A Practitioner's Approach
Verification of real-time DEVS models
SpringSim '09 Proceedings of the 2009 Spring Simulation Multiconference
Rational time-advance DEVS (RTA-DEVS)
SpringSim '10 Proceedings of the 2010 Spring Simulation Multiconference
Timed i/o test sequences for discrete event model verification
AIS'04 Proceedings of the 13th international conference on AI, Simulation, and Planning in High Autonomy Systems
Characterization of the Expressive Power of Silent Transitions in Timed Automata
Fundamenta Informaticae
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Real-time systems modeling and verification is a complex task. In many cases, formal methods have been employed to deal with the complexity of these systems, but checking those models is usually unfeasible. Modeling and simulation methods introduce a means of validating these model's specifications. In particular, Discrete Event System Specification (DEVS) models can be used for this purpose. Here, we introduce a new extension to the DEVS formalism, called the Rational Time-Advance DEVS (RTA-DEVS), which permits modeling the behavior of real-time systems that can be modeled by the classical DEVS; however, RTA-DEVS models can be formally checked with standard model-checking algorithms and tools. In order to do so, we introduce a procedure to create timed automata (TA) models that are behaviorally equivalent to the original RTA-DEVS models. This enables the use of the available TA tools and theories for formal model checking. Further, we introduce a methodology to transform classic DEVS models to RTA-DEVS models, thus enabling formal verification of classic DEVS with an acceptable accuracy.