An improved protocol test generation procedure based on UIOS
SIGCOMM '89 Symposium proceedings on Communications architectures & protocols
DEVS Formalism: A Framework for Hierarchical Model Development
IEEE Transactions on Software Engineering
Timed Wp-Method: Testing Real-Time Systems
IEEE Transactions on Software Engineering
Embedding DEVS methodology in CBD process for development of war game simulators
Proceedings of the 2007 Summer Computer Simulation Conference
Rational time-advance DEVS (RTA-DEVS)
SpringSim '10 Proceedings of the 2010 Spring Simulation Multiconference
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Model verification examines the correctness of a model implementation with respect to a model specification. While being described from model specification, implementation prepares to execute or evaluate a simulation model by a computer program. Viewing model verification as a program test this paper proposes a method for generation of test sequences that completely covers all possible behavior in specification at an I/O level. Timed State Reachability Graph (TSRG) is proposed as a means of model specification. Graph theoretical analysis of TSRG has generated a test set of timed I/O event sequences, which guarantees 100% test coverage of an implementation under test.