Theoretical Computer Science
Symbolic model checking for real-time systems
Information and Computation
Event-clock automata: a determinizable class of timed automata
Theoretical Computer Science
The time and state relationships in simulation modeling
Communications of the ACM - Special issue on simulation modeling and statistical computing
Theory of Modelling and Simulation
Theory of Modelling and Simulation
Theory of Modeling and Simulation
Theory of Modeling and Simulation
Time-Constrained Automata (Extended Abstract)
CONCUR '91 Proceedings of the 2nd International Conference on Concurrency Theory
Action Transducers and Timed Automata
CONCUR '92 Proceedings of the Third International Conference on Concurrency Theory
FORWARD AND BACKWARD SIMULATIONS PART II: TIMING-BASED SYSTEMS
FORWARD AND BACKWARD SIMULATIONS PART II: TIMING-BASED SYSTEMS
Discrete event modeling through a multi-formalism approach, from a user-oriented perspective
SpringSim '07 Proceedings of the 2007 spring simulation multiconference - Volume 2
Verification of real-time DEVS models
SpringSim '09 Proceedings of the 2009 Spring Simulation Multiconference
Rational time-advance DEVS (RTA-DEVS)
SpringSim '10 Proceedings of the 2010 Spring Simulation Multiconference
Verification of dynamically reconfigurable embedded systems by model transformation rules
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
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This paper describes several approaches to the formal verification of discrete event systems modeled with the DEVS formalism. We define the operational semantics of the DEVS formalism in terms of a timed transition system, then we characterize a subclass of DEVS models, through the definition of a formalism inspired by DEVS and timed automata, that allows the use of modelchecking tools. Finally, we discuss the application of this tools and present a simple example.