CellSs: a programming model for the cell BE architecture
Proceedings of the 2006 ACM/IEEE conference on Supercomputing
Video processing and retrieval on cell processor architecture
ICEC'07 Proceedings of the 6th international conference on Entertainment Computing
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The Cell employs a multi-core-on-chip design that integrates 9 processing elements, local memory and communication hardware into one chip. We present a source to source OpenMP compiler framework which translates the program with OpenMP directives to the necessary codes for PPE and SPE to exploit the parallelism of a sequential program through the different processing elements of the Cell. Some effective mapping strategies are also presented to conduct the thread creating and data handling between the different processors and reduce the overhead of system performance. The experimental results show that such compiler framework and mapping strategy can be effective for the heterogeneous multi-core architecture.