Evaluating Heterogeneous Memory Model by Realistic Trace-Driven Hardware/Software Co-simulation

Authors:
Wei Wang;Qigang Wang;Wei Wei;Dong Liu
Affiliations:
Intel Corporation, Beijing, P.R. China 100080 and Department of Electronic Engineering, Beijing Institute of Technology, Beijing, P.R. China 100081;Intel Corporation, Beijing, P.R. China 100080;Intel Corporation, Beijing, P.R. China 100080;Intel Corporation, Beijing, P.R. China 100080
Venue:
Euro-Par '08 Proceedings of the 14th international Euro-Par conference on Parallel Processing
Year:
2008

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Abstract

Traditional DRAM has faced more challenges in the memory subsystem. Meanwhile, more types of memories become available as new technologies have been developed in many areas. In this case, the unified memory architecture should be changed to a heterogeneous one to utilize the new memories and obtain optimal performance in terms of memory access latency and life time. In this paper, a hierarchical model is studied and compared with a flat model. To evaluate our designs, the system bus trace is collected for realistic trace-driven simulation. We use typical server benchmark SPEC jbb2005 and typical desktop benchmarks Quake 3 and SYSmark 2007 as our evaluation workloads. The experimental results show that the performance of proposed hierarchical model is very stable in writing access and its average reading access time is not sensitive to its associativity.