Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
A case for multi-level main memory
WMPI '04 Proceedings of the 3rd workshop on Memory performance issues: in conjunction with the 31st international symposium on computer architecture
ACM SIGARCH Computer Architecture News
Characterization of file I/O activity for SPEC CPU2006
ACM SIGARCH Computer Architecture News
QoS policies and architecture for cache/memory in CMP platforms
Proceedings of the 2007 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
Evaluating Heterogeneous Memory Model by Realistic Trace-Driven Hardware/Software Co-simulation
Euro-Par '08 Proceedings of the 14th international Euro-Par conference on Parallel Processing
Performance of large low-associativity caches
ACM SIGMETRICS Performance Evaluation Review
| Hi-index | 0.00 |
With the evolution of memory technologies, more types of memories are increasingly becoming available besides traditional DRAM. This paper focuses on the exploration how to organize heterogeneous memories for better performance. Two different models are introduced: Flat and Hierarchy. To evaluate our designs, the system bus trace is collected for trace-driven simulation. We use applications from SPEC jbb2005 and SPEC CPU2006 suite - typical server and desktop benchmark applications to compare the two models. It is shown that Hierarchical model can save much time in writing access and the average reading access time of it may longer or shorter than that of Flat according to the heterogeneous memory parameters. The Hierarchical model may also help to extend the life time of lower level memory while the Flat model can be used in a QoS enabled environment. Another contribution of our work is the recommended memory parameters in building the Hierarchical model.