Unified Methods for VLSI Simulation and Test Generation
Unified Methods for VLSI Simulation and Test Generation
Proceedings of the Applications of Evolutionary Computing on EvoWorkshops 2002: EvoCOP, EvoIASP, EvoSTIM/EvoPLAN
The Intrinsic Evolution of Virtex Devices Through Internet Reconfigurable Logic
ICES '00 Proceedings of the Third International Conference on Evolvable Systems: From Biology to Hardware
ICES '00 Proceedings of the Third International Conference on Evolvable Systems: From Biology to Hardware
The Test Vector Problem and Limitations to Evolving Digital Circuits
EH '00 Proceedings of the 2nd NASA/DoD workshop on Evolvable Hardware
Safe Intrinsic Evolution of Virtex Devices
EH '00 Proceedings of the 2nd NASA/DoD workshop on Evolvable Hardware
A Genetic Algortithm for Automatic Generation of Test Logic for Digital Circuits
ICTAI '96 Proceedings of the 8th International Conference on Tools with Artificial Intelligence
Extrinsic evolvable hardware on the RISA architecture
ICES'07 Proceedings of the 7th international conference on Evolvable systems: from biology to hardware
Explorations in design space: unconventional electronics designthrough artificial evolution
IEEE Transactions on Evolutionary Computation
A module-level three-stage approach to the evolutionary design of sequential logic circuits
Genetic Programming and Evolvable Machines
Hi-index | 0.01 |
Evolution is particularly good at finding specific solutions, which are only valid for exactly the input and environment that are presented during evolution. In most evolution experiments the input pattern order problemis not considered, even though the ability to provide a correct result for any input pattern is a prerequisite for valid circuits. Therefore, the importance of including randomness in the input pattern applied during evolution is addressed in this paper. This is shown to be mandatory--particularly in the case of unconstrained intrinsic evolution of digital circuits--in order to find valid solutions. The different ways in which unconstrained evolution and constrained evolution exploit resources of a hardware substrate are compared. It is also shown that evolution benefits from versatile input configurations. Furthermore, hierarchical fitness functions, previously introduced to improve the evolution of combinatorial circuits, are applied to the evolution of sequential circuits.