Digital and analog communication systems (5th ed.)
Digital and analog communication systems (5th ed.)
An Aliasing-Free Receiver with Variable Sample Rate Digital Feedback M/T NDA Timing Synchronization
Wireless Personal Communications: An International Journal
Synchronization in Software Radios-Carrier and Timing Recovery Using FPGAs
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
FPGA Implementation of Carrier Synchronization for QAM Receivers
Journal of VLSI Signal Processing Systems
Wireless Personal Communications: An International Journal
DSD '07 Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools
A self-normalizing symbol synchronization lock detector for QPSK and BPSK
IEEE Transactions on Wireless Communications
IEEE Communications Magazine
Rapidradio: a domain-specific productivity enhancing framework
International Journal of Reconfigurable Computing - Special issue on selected papers from ReconFig 2009 International conference on reconfigurable computing and FPGAs (ReconFig 2009)
On the Implementation of a Quasi-Generic Synchronization Architecture for Linear Digital Modulations
Journal of Signal Processing Systems
RapidRadio: Signal Classification and Radio Deployment Framework
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on CAPA'09, Special Section on WHS'09, and Special Section VCPSS' 09
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This paper presents an efficient and optimized carrier phase independent programmable Symbol Timing Recovery (STR) circuit. The novel structure is highly versatile. In fact, it can be configured at runtime to work in different conditions. All BPSK, QPSK and OQPSK modulations are supported thanks to runtime variable control coefficients. This approach also provides flexibility in performances and support for different sampling rates. The proposed circuit is presented in a Digital PLL loop structure and it is designed according to the Software Defined Radio (SDR) philosophy, which requires ever more flexible communication solutions able to support different protocols and standards. High performances are reached by the proposed hardware implementation, moreover, flexibility is guaranteed by the configurable architecture. When implemented with a Xilinx XC4VLX60 FPGA chip, the new circuit reaches the maximum running frequency of 108.7MHz, thus sustaining a symbol rate of 10MSps when 10 samples per symbol are employed.