FPGA Implementation of Carrier Synchronization for QAM Receivers

  • Authors:

  • Chris Dick;Fred Harris;Michael Rice

  • Affiliations:

  • Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124, USA;CUBIC Signal Processing Chair, College of Engineering, San Diego State University, CA 92182, USA;Department of Electrical and Computer Engineering, Brigham Young University, Provo, UT 84602, USA

  • Venue:
  • Journal of VLSI Signal Processing Systems
  • Year:
  • 2004

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Abstract

Software defined radios (SDR) are highly configurable hardware platforms that provide the technology for realizing the rapidly expanding third (and future) generation digital wireless communication infrastructure. While there are a number of silicon alternatives available for implementing the various functions in a SDR, field programmable gate arrays (FPGAs) are an attractive option for many of these tasks for reasons of performance, power consumption and flexibility. Amongst the more complex tasks performed in a high data rate wireless system is synchronization. This paper examines carrier synchronization in SDRs using FPGA based signal processors. We provide a tutorial style overview of carrier recovery techniques for QPSK and QAM modulation schemes and report on the design and FPGA implementation of a carrier recovery loop for a 16-QAM modern. Two design alternatives are presented to highlight the rich design space accessible using configurable logic. The FPGA device utilization and performance for a carrier recovery circuit using a look-up table approach and CORDIC arithmetic are presented. The simulation and FPGA implementation process using a recent system level design tool called System Generator™ for DSP described.