A methodology and a case-study for network-on-chip based MP-SoC architectures

Authors:
Sergio V. Tota;Mario R. Casu;Paolo Motto;Massimo Ruo Roch;Maurizio Zamboni
Affiliations:
VLSI LAB, Politecnico di Torino, Italy;VLSI LAB, Politecnico di Torino, Italy;VLSI LAB, Politecnico di Torino, Italy;VLSI LAB, Politecnico di Torino, Italy;VLSI LAB, Politecnico di Torino, Italy
Venue:
Proceedings of the 2nd international conference on Nano-Networks
Year:
2007

Citing 6
Cited 0

Routing in communications networks

Routing in communications networks
The SPLASH-2 programs: characterization and methodological considerations

ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
NOC Application programming interfaces: high level communication primitives and operating system services for power management

Networks on chip
An Efficient On-Chip Network Interface Offering Guaranteed Services, Shared-Memory Abstraction, and Flexible Network Configuration

Proceedings of the conference on Design, automation and test in Europe - Volume 2
Æthereal Network on Chip: Concepts, Architectures, and Implementations

IEEE Design & Test
Implementation analysis of NoC: a MPSoC trace-driven approach

GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI

Quantified Score

Hi-index	0.00

Visualization

Abstract

The many-core design paradigm requires flexible and modular hardware and software components to provide the required scalability of next-generation on-chip multiprocessor architectures. A multidisciplinary approach is necessary to consider all the interactions between the different components of the design. In this work a complete design methodology is proposed, tackling at once the aspects of hardware architecture, programming model and design automation. The proposed design flow has been used in the implementation of a multiprocessor Network-on-Chip based system, the NoCRay graphic accelerator. The system uses 8 Tensilica LX processors and has been physically implemented on a Xilinx Virtex-4 LX-160 FPGA reporting a 17.3M equivalent gate-count. Performance are compared with a commercial general purpose processor and show good results considering the low frequency of the prototype.