New non-volatile memory structures for FPGA architectures

Authors:
David Choi;Kyu Choi;John D. Villasenor
Affiliations:
Electrical Engineering Department, University of California, Los Angeles, CA;O2IC Company Ltd, Santa Clara, CA;Electrical Engineering Department, University of California, Los Angeles, CA
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2008

Citing 6
Cited 0

Architecture and CAD for Deep-Submicron FPGAs

Architecture and CAD for Deep-Submicron FPGAs
An FPGA Implementation for a High Throughput Adaptive Filter Using Distributed Arithmetic

FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Duty Cycle Aware Application Design using FPGAs

FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Exploring technology alternatives for nano-scale FPGA interconnects

Proceedings of the 42nd annual Design Automation Conference
A 90nm low-power FPGA for battery-powered applications

Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Circuits and architectures for field programmable gate array with configurable supply voltage

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

A new set of programmable elements (PEs) using a new non-volatile device for use with routing switches and logical elements within a field-programmable gate array (FPGA) is described. The PEs have small area, can be combined with components that use low operational voltage on the same CMOS logic process, are non-volatile, enable the use of fast thin-oxide pass transistors, and are reprogrammable. A novel non-volatile flip-flop for use within the logical elements is presented as well. In combination, these methods enable programmable logic devices with improved area efficiency, the speed advantages of SRAM-based FPGAs, and a wide range of opportunities for power down strategies.