Continuous-time delta-sigma modulators for high-speed A/D conversion: theory, practice and fundamental performance limits
Bandpass delta-sigma data converters
ASILOMAR '95 Proceedings of the 29th Asilomar Conference on Signals, Systems and Computers (2-Volume Set)
A 1-GSPS CMOS Flash A/D Converter for System-on-Chip Applications
WVLSI '01 Proceedings of the IEEE Computer Society Workshop on VLSI 2001
An ultra low area asynchronous combo 4/8/12-bit/quaternary A/D converter based on integer division
Microelectronics Journal
Detailed analysis of the effect of a hysteretic quantizer in a multibit, Sigma-Delta modulator
Microelectronics Journal
A 1.2V, 130nm CMOS parallel continuous-time ΣΔ ADC for OFDM UWB receivers
Microelectronics Journal
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In this work the design of a continuous-time @D@S modulator for Gigabit Ethernet applications is presented. The input bandwidth and oversampling ratio are, respectively, 62.5MHz and 8, resulting in a clock frequency of 1GHz. It was designed and implemented in a standard 90nm CMOS technology. The active area of the modulator measures 0.0207mm^2. It consists of a loop filter based on RC-opamp integrators and a 3-bit quantizer which includes a data weighted averaging scrambler. A digital tuning scheme to deal with process variations has also been included. System level simulations including several non-ideal effects have been carried out in order to determine in detail the performance of the converter. Experimental results show a resolution of 7.1 effective bits, and a power consumption of 10.8mW from a nominal power supply of 1V.