A 1.2V, 130nm CMOS parallel continuous-time ΣΔ ADC for OFDM UWB receivers

Authors:
Jokin Segundo;Jesús Arias;Luis Quintanilla;Lourdes Enríquez;Jesús M. Hernández;José Vicente
Affiliations:
Departamento de Electricidad y Electrónica, E. T. S. I. de Telecomunicación, Paseo de Belén 15, Universidad de Valladolid, 47011 Valladolid, Spain;Departamento de Electricidad y Electrónica, E. T. S. I. de Telecomunicación, Paseo de Belén 15, Universidad de Valladolid, 47011 Valladolid, Spain;Departamento de Electricidad y Electrónica, E. T. S. I. de Telecomunicación, Paseo de Belén 15, Universidad de Valladolid, 47011 Valladolid, Spain;Departamento de Electricidad y Electrónica, E. T. S. I. de Telecomunicación, Paseo de Belén 15, Universidad de Valladolid, 47011 Valladolid, Spain;Departamento de Electricidad y Electrónica, E. T. S. I. de Telecomunicación, Paseo de Belén 15, Universidad de Valladolid, 47011 Valladolid, Spain;Departamento de Electricidad y Electrónica, E. T. S. I. de Telecomunicación, Paseo de Belén 15, Universidad de Valladolid, 47011 Valladolid, Spain
Venue:
Microelectronics Journal
Year:
2012

Citing 7
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Abstract

The design and implementation in a 1.2V, 130nm CMOS technology of a parallel continuous-time @S@D modulator for OFDM UWB signals is described. Once the parallel architecture and the metrics used are presented, the NTF is optimized and implemented using a third order lowpass and a fourth order bandpass modulator. Both are CRFB structures which use active-RC integrators. Then, the circuital blocks are discussed and some comments about the test set-up are given. Experimental results show good agreement with both system-level and layout-level simulations, with up to 15dB DR for QPSK modulation over a signal bandwidth of 528MHz, with a 62.3mW power consumption.