Hierarchical Parallelization of an H.264/AVC Video Encoder
PARELEC '06 Proceedings of the international symposium on Parallel Computing in Electrical Engineering
A Highly Efficient Parallel Algorithm for H.264 Encoder Based on Macro-Block Region Partition
HPCC '07 Proceedings of the 3rd international conference on High Performance Computing and Communications
An evaluation of parallelization concepts for baseline-profile compliant H.264/AVC decoders
Euro-Par'07 Proceedings of the 13th international Euro-Par conference on Parallel Processing
Development of a high-level simulation approach and its application to multicore video decoding
IEEE Transactions on Circuits and Systems for Video Technology
A QHD-capable parallel H.264 decoder
Proceedings of the international conference on Supercomputing
A study of 3D Network-on-Chip design for data parallel H.264 coding
Microprocessors & Microsystems
Parallel HEVC Decoding on Multi- and Many-core Architectures
Journal of Signal Processing Systems
Architectural Decomposition of Video Decoders by Meansof an Intermediate Data Stream Format
Journal of Signal Processing Systems
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The high computational demands of the H.264 decoding process pose serious challenges on current processor architectures. A natural way to tackle this problem is the use of multi-core systems. The contribution of this paper lies in a systematic overview and performance evaluation of parallel video decoding approaches. Our study investigates six methods for accomplishing data-parallel splitting in strongly resource-restricted environments inherent to mobile devices. These methods are compared against each other in terms of run-time complexity, core usage, inter-communication and bus transfers. We present benchmark results using different numbers of processor cores. Our results shall aid in finding a splitting strategy that is best suited for the targeted hardware-architecture.