A reconfigurable VLSI architecture for a database processor

  • Authors:
  • Kemal Oflazer

  • Affiliations:
  • Carnegie-Mellon University, Pittsburgh, Pennsylvania

  • Venue:
  • AFIPS '83 Proceedings of the May 16-19, 1983, national computer conference
  • Year:
  • 1983

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Abstract

This work brings together the processing potential offered by regularly structured VLSI processing units and the architecture of a database processor---the Relational Associative Processor (RAP). The main motivations are to integrate a RAP cell processor on a few VLSI chips and improve performance by employing procedures exploiting these VLSI chips and the system level reconfigurability of processing resources. The resulting VLSI database processor consists of parallel processing cells that can be reconfigured into a large processor to execute the hard operations of projection and semijoin efficiently. It is shown that such a configuration can provide 2 to 3 orders of magnitude of performance improvement over previous implementations of the RAP system in the execution of such operations.