Application of neural networks and genetic algorithms to the screening for high quality chips

  • Authors:

  • Chenn-Jung Huang;You-Jia Chen;Chi-Feng Wu;Yi-An Huang

  • Affiliations:

  • Department of Computer Science and Information Engineering, National Dong Hwa University, No. 123 Hua-Hsi Rd., Hualien 970, Taiwan;Department of Computer Science and Information Engineering, National Dong Hwa University, No. 123 Hua-Hsi Rd., Hualien 970, Taiwan;Testing Factory, Philips Semiconductor Kaohsiung, Taiwan;Testing Factory, Philips Semiconductor Kaohsiung, Taiwan

  • Venue:
  • Applied Soft Computing
  • Year:
  • 2009

Quantified Score

Hi-index 0.00

Visualization

Abstract

During electrical testing, each die on a wafer must be tested to determine whether it functions as originally designed. For a clustered defect on a wafer, for example scratches, stains, or localized failure patterns, defective dies in the flawed area may not all be detected during the electrical testing stage. To prevent the defective dies from proceeding to the final assembly, the testing factory must assign some workers to identify patterns in the layout of defective dies for labeling other potential defects. Although a previously developed defect detection program enables full automation of the testing process in a testing factory, numerous defective dies in recognized clusters are not picked out, or in some clusters are even not captured in certain circumstances. This work thus proposes two automatic wafer-scale defect cluster identifiers, which utilize neural networks and genetic algorithms for detecting the defect clusters, and compares them with that presented in our earlier work. The experimental results confirm that both of the proposed algorithms are more effective in identifying defect clusters than the defect detection program presently used by the testing factory.