Comparing algorithm for dynamic speed-setting of a low-power CPU
MobiCom '95 Proceedings of the 1st annual international conference on Mobile computing and networking
The simulation and evaluation of dynamic voltage scaling algorithms
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Performance Measurement Intrusion and Perturbation Analysis
IEEE Transactions on Parallel and Distributed Systems
Software Power Estimation and Optimization for High Performance, 32-bit Embedded Processors
ICCD '98 Proceedings of the International Conference on Computer Design
Policies for dynamic clock scheduling
OSDI'00 Proceedings of the 4th conference on Symposium on Operating System Design & Implementation - Volume 4
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In this paper we introduce a novel approach for measuring and estimating effect of performance scaling for user interface latency and power consumption. Growing demand for higher performance in battery powered devices such laptop PC's has spawned techniques for dynamically decreasing performance in order to save energy and yet preserve high peak performance. For the evaluation of this approach we analyse system that uses dynamic voltage and frequency scaling technology for reducing power consumption based on CPU load. We focus on analysing effect of different parameters of the dynamic performance scaling such as length of time between load predictions. By using this measurement approach we were able to distinguish clear differences in energy consumption as well as in user interface performance.