A context switching streaming memory architecture to accelerate a neocortex model

Authors:
Christopher N. Vutsinas;Tarek M. Taha;Kenneth L. Rice
Affiliations:
Department of Electrical and Computer Engineering, Clemson University, Riggs Hall, P.O. Box 340915, Clemson, SC 29634, USA;Department of Electrical and Computer Engineering, Clemson University, Riggs Hall, P.O. Box 340915, Clemson, SC 29634, USA;Department of Electrical and Computer Engineering, Clemson University, Riggs Hall, P.O. Box 340915, Clemson, SC 29634, USA
Venue:
Microprocessors & Microsystems
Year:
2009

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Abstract

A novel architecture to accelerate a neocortex inspired cognitive model is presented. The architecture utilizes a collection of context switchable processing elements (PEs). This enables time multiplexing of nodes in the model onto available PEs. A streaming memory system is designed to enable high-throughput computation and efficient use of memory resources. Several scheduling algorithms were examined to efficiently assign network nodes to the PEs. Multiple parallel FPGA-accelerated implementations were evaluated on a Cray XD1. Networks of varying complexity were tested and indicate that hardware acceleration can provide an average throughput gain of 184 times over equivalent parallel software implementations.