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IEEE Transactions on Computers
Motion Adaptive De-interlacing with Local Scene Changes Detection
ICICIC '07 Proceedings of the Second International Conference on Innovative Computing, Informatio and Control
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IEEE Transactions on Consumer Electronics
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IEEE Transactions on Consumer Electronics
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IEEE Transactions on Consumer Electronics
An effective de-interlacing technique using motion compensated interpolation
IEEE Transactions on Consumer Electronics
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IEEE Transactions on Consumer Electronics
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IEEE Transactions on Consumer Electronics
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IEEE Transactions on Consumer Electronics
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IEEE Transactions on Consumer Electronics
A motion-adaptive de-interlacing method using an efficient spatial and temporal interpolation
IEEE Transactions on Consumer Electronics
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IEEE Transactions on Consumer Electronics
Efficient de-interlacing technique by inter-field information
IEEE Transactions on Consumer Electronics
De-interlacing algorithms based on motion compensation
IEEE Transactions on Consumer Electronics
Deinterlacing by successive approximation
IEEE Transactions on Image Processing
IEEE Transactions on Circuits and Systems for Video Technology
A robust scene-change detection method for video segmentation
IEEE Transactions on Circuits and Systems for Video Technology
An edge-preserving motion-compensated approach for video deinterlacing
FMN'10 Proceedings of the Third international conference on Future Multimedia Networking
An adaptive motion-compensated approach for video deinterlacing
Multimedia Tools and Applications
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Scene changes occur frequently in film broadcasting, and tend to destabilize the performance with blurred, jagged, and artifacts effects when de-interlacing methods are utilized. This paper presents an efficient VLSI architecture of video de-interlacing with considering scene change to improve the quality of video results. This de-interlacing architecture contains three main parts. The first is scene change detection, which is designed based on examining the absolute pixel difference value of two adjacent even or odd fields. The second is background index mechanism for classifying motion and non-motion pixels of input field. The third component, spatial-temporal edge-based median filter, is used to deal with the interpolation for those motion pixels. Comparing with the existed de-interlacing approaches, our architecture design can significantly ameliorate the PSNRs of the video sequences with various scene changes; for other situations, it also maintains better performances. The proposed architecture has been implemented as a VLSI chip based on UMC 0.18-μm CMOS technology process. The total gate count is 30114 and its layout area is about 710 × 710-μm. The power consumption is 39.78 mW at working frequency 128.2 MHz, which is able to process de-interlacing for HDTV in real-time.