Design of Analog CMOS Integrated Circuits
Design of Analog CMOS Integrated Circuits
Phase noise on a 2-GHz CMOS LC oscillator
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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A design of a low-power CMOS ring oscillator for an application to a 13.56 MHz clock generator in an implantable RFID tag is proposed. The circuit is based on a novel voltage inverter, which is an improved version of the conventional current-source loaded inverter. The proposed circuit enables low-power operation and low sensitivity of the oscillation frequency, fOSC, to decay of the power supply VDD. By employing a gm-boosting subcircuit, power dissipation is decreased to 49 μW at fOSC = 13.56 MHz. The sensitivity of fOSC to VDD is reduced to -0.02 at fOSC = 13.56 MHz thanks to the use of composite high-impedance current sources.