Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
Performance Modelling with Deterministic and Stochostic Petri Nets
Performance Modelling with Deterministic and Stochostic Petri Nets
Generalized Stochastic Petri Nets: A Definition at the Net Level and its Implications
IEEE Transactions on Software Engineering
A Characterization of the Stochastic Process Underlying a Stochastic Petri Net
IEEE Transactions on Software Engineering
Performance analysis of multistage interconnection networks with a new high-level net model
Journal of Systems Architecture: the EUROMICRO Journal
Application of deterministic and stochastic Petri-Nets for performance modeling of NoC architectures
Journal of Systems Architecture: the EUROMICRO Journal
CPN tools for editing, simulating, and analysing coloured Petri nets
ICATPN'03 Proceedings of the 24th international conference on Applications and theory of Petri nets
Modeling noc architectures by means of deterministic and stochastic petri nets
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
NoC simulation modeling in DEVS-suite
Proceedings of the 2011 Symposium on Theory of Modeling & Simulation: DEVS Integrative M&S Symposium
Hi-index | 0.00 |
Network-on-Chip (NoC) is proposed as a new scalable architecture to address the future design challenges of system-on-a-chip (SoC). As current verification techniques for on-chip communication algorithms are typically complicated tasks including many hardware modules and software routines, verifying the algorithms themselves is almost impossible. Having the incentive for simplifying verification of these on-chip algorithms, in this paper, we propose a detailed NoC CPN model in which key NoC networking challenges, namely network topology, switching method, and routing algorithm are considered. By this model, any desired NoC topologies, including but not limited to, mesh and k-ary n-cube can be constructed. As for switching techniques, dominant on-chip switching methods, namely, packet switching, circuit switching, and wormhole switching, are modeled. Besides, as model of a NoC switch element is highly dependent on its switch fabric type, different sorts of switching fabrics, i.e., crossbar and shared bus, are modeled in this contribution. For routing the packets between cores, a CPN version of dimension-ordered routing, dominant routing algorithm for NoC, is implemented in the switches.