AMPLE: An Adaptive Multi-Performance Processor for Low-Energy Embedded Applications

  • Authors:

  • Tohru Ishihara;Seiichiro Yamaguchi;Yuriko Ishitobi;Tadayuki Matsumura;Yuji Kunitake;Yuichiro Oyama;Yusuke Kaneda;Masanori Muroyama;Toshinori Sato

  • Affiliations:

  • System LSI Research Center, Kyushu University, 3-8-33, Momochihama, Sawara-ku, Fukuoka, 814-0001 JAPAN. ishihara@slrc.kyushu-u.ac.jp;Graduate School of Information Science and Electrical Engineering, Kyushu University, 744 Motooka, Nishi-ku, Fukuoka, 819-0395 JAPAN. seiichiro@c.csce.kyushu-u.ac.jp;Graduate School of Information Science and Electrical Engineering, Kyushu University, 744 Motooka, Nishi-ku, Fukuoka, 819-0395 JAPAN. ishitobi@c.csce.kyushu-u.ac.jp;Graduate School of Information Science and Electrical Engineering, Kyushu University, 744 Motooka, Nishi-ku, Fukuoka, 819-0395 JAPAN. matsumura@c.csce.kyushu-u.ac.jp;Graduate School of Information Science and Electrical Engineering, Kyushu University, 744 Motooka, Nishi-ku, Fukuoka, 819-0395 JAPAN. y-kunitake@c.csce.kyushu-u.ac.jp;Graduate School of Information Science and Electrical Engineering, Kyushu University, 744 Motooka, Nishi-ku, Fukuoka, 819-0395 JAPAN. yuichiro@c.csce.kyushu-u.ac.jp;Graduate School of Information Science and Electrical Engineering, Kyushu University, 744 Motooka, Nishi-ku, Fukuoka, 819-0395 JAPAN. kaneda@c.csce.kyushu-u.ac.jp;System LSI Research Center, Kyushu University, 3-8-33, Momochihama, Sawara-ku, Fukuoka, 814-0001 JAPAN. muroyama@slrc.kyushu-u.ac.jp;System LSI Research Center, Kyushu University, 3-8-33, Momochihama, Sawara-ku, Fukuoka, 814-0001 JAPAN. tsato@slrc.kyushu-u.ac.jp

  • Venue:
  • SASP '08 Proceedings of the 2008 Symposium on Application Specific Processors
  • Year:
  • 2008

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Abstract

This paper proposes an energy efficient processor which can be used as a design alternative for the dynamic voltage scaling (DVS) processors in embedded system design. The processor consists of multiple PE (processing element) cores and a selective set-associative cache memory. The PE-cores have the same instruction set architecture but differ in their clock speeds and energy consumptions. Only a single PE-core is activated at a time and the other PE-cores are deactivated using clock gating and signal gating techniques. The major advantage over the DVS processors is a small overhead for changing its performance. The gate-level simulation demonstrates that our processor can change its performance within 1.5 microsecond and dissipates about 10 nanojoule while conventional DVS processors need hundreds of microseconds and dissipate a few microjoule for the performance transition [1, 2].