FPGA-based ROM-free network intrusion detection using shift-OR circuit

Authors:
Wen-Jyi Hwang;Huang-Chun Roan;Ying-Nan Shih;Chia-Tien Dan Lo;Chien-Min Ou
Affiliations:
(Correspd. Tel.: +886 2 2932 2411 201/ Fax: +886 2 2932 2378/ E-mail: whwang@ntnu.edu.tw) Department of Computer Science and Information Engineering, National Taiwan Normal University, Taipei, 117 ...;Department of Computer Science and Information Engineering, National Taiwan Normal University, Taipei, 117, Taiwan;Department of Computer Science and Information Engineering, National Taiwan Normal University, Taipei, 117, Taiwan;Department of Computer Science, University of Texas at San Antonio, San Antonio, TX 78249, USA;Department of Electronics Engineering, Ching Yun University, Chungli, 320, Taiwan
Venue:
Journal of Embedded Computing - Design and Optimization for High Performance Embedded Systems
Year:
2009

Citing 9
Cited 2

A new approach to text searching

Communications of the ACM
Granidt: Towards Gigabit Rate Network Intrusion Detection Technology

FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Assisting Network Intrusion Detection with Reconfigurable Hardware

FCCM '02 Proceedings of the 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Implementation of a Content-Scanning Module for an Internet Firewall

FCCM '03 Proceedings of the 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Deep Packet Filter with Dedicated Logic and Read Only Memories

FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Scalable Pattern Matching for High Speed Networks

FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Pre-Decoded CAMs for Efficient and High-Speed NIDS Pattern Matching

FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
A Signature Match Processor Architecture for Network Intrusion Detection

FCCM '05 Proceedings of the 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Efficient logic circuit for network intrusion detection

EUC'06 Proceedings of the 2006 international conference on Embedded and Ubiquitous Computing

String alignment pre-detection using unique subsequences for FPGA-based network intrusion detection

Computer Communications
An enhanced architecture for pattern matching in FPGA for intrusion detection in wireless sensor networks

International Journal of Mobile Network Design and Innovation

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper introduces a novel FPGA-based signature match co-processor that can serve as the core of a hardware-based network intrusion detection system (NIDS). The co-processor is based on simple shift registers and bitmap encoders for the efficient signature match in hardware. As compared with related work, experimental results show that the proposed work achieves higher throughput and less hardware resource in the FPGA implementations of NIDS systems.