Efficient logic circuit for network intrusion detection

Authors:
Huang-Chun Roan;Chien-Min Ou;Wen-Jyi Hwang;Chia-Tien Dan Lo
Affiliations:
Graduate Institute of Computer Science and Information Engineering, National Taiwan Normal University, Taipei, Taiwan;Department of Electronics Engineering, Ching Yun University, Chungli, Taiwan;Graduate Institute of Computer Science and Information Engineering, National Taiwan Normal University, Taipei, Taiwan;Department of Computer Science, University of Texas at San Antonio, San Antonio, TX
Venue:
EUC'06 Proceedings of the 2006 international conference on Embedded and Ubiquitous Computing
Year:
2006

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Abstract

A novel architecture for a hardware-based network intrusion detection system (NIDS) is presented in this paper. The system adopts an FPGA-based signature match co-processor as a core for the NIDS. The signature matcher is based on an algorithm that employs simple shift registers, or-gates, and ROMs in which patterns are stored. As compared with related work, experimental results show that the proposed work achieves higher throughput and less hardware resource in the FPGA implementations of network intrusion detection