Dynamic power consumption in Virtex™-II FPGA family
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RTCSA '05 Proceedings of the 11th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications
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IPSN '05 Proceedings of the 4th international symposium on Information processing in sensor networks
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IEEE Wireless Communications
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In this paper, we present preliminary results regarding the data processing approach to energy efficiency of wireless and untethered field programmable gate array (FPGA)-based embedded systems. Re-configurability of FPGA allows for significant flexibility in its applications to embedded systems. However, high power consumption (caused by such flexibility) influences the designing process significantly. Moreover, radio communication adds additional power consumption to the overall energy budget. We present few ideas (addressing local data processing versus communicating processed data) that are envisaged to decrease the total energy spent on communicating data bits. Energy efficiency is addressed at the high-level of the designing process (the system-level). It is envisaged that results of our experiments can be also applied to other embedded systems applications, not limited to FPGA-based only.