Minimum probability of error for asynchronous Gaussian multiple-access channels
IEEE Transactions on Information Theory
Matrix datapath architecture for an iterative 4x4 MIMO noise whitening algorithm
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Modular design of a large sorting network
ISPAN '97 Proceedings of the 1997 International Symposium on Parallel Architectures, Algorithms and Networks
Advanced receiver algorithms for MIMO wireless communications
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Algorithm and implementation of the K-best sphere decoding for MIMO detection
IEEE Journal on Selected Areas in Communications
| Hi-index | 0.00 |
Multiple-input multiple-output (MIMO) systems are of significant interest due to their ability to increase the capacity of wireless communications systems, but for these to be useful they must also be practical for implementation in VLSI circuits. A particularly difficult part of these systems is the detector, where the optimal maximum-likelihood solution is desirable, but cannot be directly implemented due to its exponential complexity. This paper addresses this challenge and presents a digital circuit design for an 8脳8 MIMO detection problem. A key feature is the integrated channel preprocessing unit, which performs the channel decomposition functions that are either omitted or performed "off-line" in other designs. The proposed device achieves near maximum likelihood bit error rate results at 57.6 Mbps. Other novelties include a high speed sorting mechanism and power saving features.