Property specification patterns for finite-state verification
FMSP '98 Proceedings of the second workshop on Formal methods in software practice
Automata-Based Verification of Temporal Properties on Running Programs
Proceedings of the 16th IEEE international conference on Automated software engineering
The Evolution of SystemVerilog
IEEE Design & Test
Pinapa: an extraction tool for SystemC descriptions of systems-on-a-chip
Proceedings of the 5th ACM international conference on Embedded software
Introspection Mechanisms for Semi-Formal Verification in a System-Level Design Environment
RSP '06 Proceedings of the Seventeenth IEEE International Workshop on Rapid System Prototyping
A new efficient EDA tool design methodology
ACM Transactions on Embedded Computing Systems (TECS)
The temporal logic of programs
SFCS '77 Proceedings of the 18th Annual Symposium on Foundations of Computer Science
Reasoning about infinite computation paths
SFCS '83 Proceedings of the 24th Annual Symposium on Foundations of Computer Science
Efficient monitoring of ω-languages
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
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A new generation of computer-aided design (CAD) tools is mandatory to cope with the growing complexity of System-On-Chip. We believe that they should be built on top of a modern and standard framework. ESys.NET is a design environment based on the .NET Framework. It takes advantage of advanced programming features which facilitates the integration of external tools. This paper presents a runtime verification tool for ESys.NET. Introspection ability is emphasized together with its capabilities to cooperate with third party tools. Introspection is used to retrieve the state of the model during simulation and to check a set of user defined properties. Neither the model nor the simulator is modified by the verification process. Experimentations on an AMBA bus model highlight the effectiveness of this approach.