Multilevel full-chip routing for the X-based architecture
Proceedings of the 42nd annual Design Automation Conference
Efficient Rectilinear Steiner Tree Construction with Rectilinear Blockages
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Physical Design for 3D System on Package
IEEE Design & Test
Computational Geometry: Algorithms and Applications
Computational Geometry: Algorithms and Applications
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Due to emerging DSM effects, routing has been a very important topic in current design flow. Currently there are three issues. One, the traditional Manhattan routing has longer length and larger delay than X-architecture routing. Second, in multilayer routing, the delay of one via is much larger than the delay of Manhattan routing. Third, since a routed segment and macro cell should be considered as obstacles, we must consider the rectangle and non-rectangle obstacles, and consider the number of vias as well. In this paper, under the conditions of rectangle obstacles and non-rectangle obstacles, we use fewer vias and X-Architecture router by region to construct the multilayer routing trees. The main purpose is to obtain a routing tree of minimal wirelength and minimal delay.