Analysis and Design of Analog Integrated Circuits
Analysis and Design of Analog Integrated Circuits
Novel hybrid D/A structures for high-resolution SAR ADCs-analysis, modeling and realization
Microelectronics Journal
A charge-pump and comparator based power-efficient pipelined ADC technique
Microelectronics Journal
A 24.5 mW, 10-bit, 50 MS/sec CMOS pipelined analogue-to-digital converter
International Journal of High Performance Systems Architecture
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A systematic design approach for low-power 10-bit, 100MS/s pipelined analog-to-digital converter (ADC) is presented. At architectural level various per-stage-resolution are analyzed and most suitable architecture is selected for designing 10-bit, 100MS/s pipeline ADC. At Circuit level a modified wide-bandwidth and high-gain two-stage operational transconductance amplifier (OTA) proposed in this work is used in track-and-hold amplifier (THA) and multiplying digital-to-analog converter (MDAC) sections, to reduce power consumption and thermal noise contribution by the ADC. The signal swing of the analog functional blocks (THA and MDAC sections) is allowed to exceed the supply voltage (1.8V), which further increases the dynamic range of the circuit. Charge-sharing comparator is proposed in this work, which reduces the dynamic power dissipation and kickback noise of the comparator circuit. The bootstrap technique and bottom plate sampling technique is employed in THA and MDAC sections to reduce the nonlinearity error associated with the input signal resulting in a signal-to-noise-distortion ratio of 58.72/57.57dB at 2MHz/Nyquist frequency, respectively. The maximum differential nonlinearity (DNL) is +0.6167/-0.3151LSB and the maximum integral nonlinearity (INL) is +0.4271/-0.4712LSB. The dynamic range of the ADC is 58.72dB for full-scale input signal at 2MHz input frequency. The ADC consumes 52.6mW at 100MS/s sampling rate. The circuit is implemented using UMC-180nm digital CMOS technology.