A systematic design approach for low-power 10-bit 100MS/s pipelined ADC
Microelectronics Journal
High speed, high resolution and low power approaches for SAR A/D converter
WiCOM'09 Proceedings of the 5th International Conference on Wireless communications, networking and mobile computing
Adaptive successive approximation ADC for biomedical acquisition system
Microelectronics Journal
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An intermittent-sleeping C-R hybrid D/A structure, a resistor-reusing R-C hybrid D/A structure and an R-C-R combined D/A structure are researched with theoretical analysis and Matlab modeling in this paper. The switching power and passive components' matching requirement of these D/A structures are discussed in detail. Three SAR ADCs with these three novel structures are realized based on SMIC 0.18@mm CMOS, SMIC 90nm CMOS and UMC 90nm CMOS, respectively. The theoretical analysis, modeling verification and circuit realization proves the applicability of these three D/A conversion networks to high-resolution SAR ADCs.